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Freescale Semiconductor /MK10F12 /SIM /SOPT7

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Interpret as SOPT7

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000)ADC0TRGSEL 0 (0)ADC0PRETRGSEL 0 (0)ADC0ALTTRGEN 0 (0000)ADC1TRGSEL 0 (0)ADC1PRETRGSEL 0 (0)ADC1ALTTRGEN 0 (0000)ADC2TRGSEL 0 (0)ADC2PRETRGSEL 0 (0)ADC2ALTTRGEN 0 (0000)ADC3TRGSEL 0 (0)ADC3PRETRGSEL 0 (0)ADC3ALTTRGEN

ADC2PRETRGSEL=0, ADC1TRGSEL=0000, ADC1ALTTRGEN=0, ADC0ALTTRGEN=0, ADC0PRETRGSEL=0, ADC3ALTTRGEN=0, ADC3PRETRGSEL=0, ADC3TRGSEL=0000, ADC1PRETRGSEL=0, ADC0TRGSEL=0000, ADC2TRGSEL=0000, ADC2ALTTRGEN=0

Description

System Options Register 7

Fields

ADC0TRGSEL

ADC0 trigger select

0 (0000): External trigger

1 (0001): High speed comparator 0 asynchronous interrupt

2 (0010): High speed comparator 1 asynchronous interrupt

3 (0011): High speed comparator 2 asynchronous interrupt

4 (0100): PIT trigger 0

5 (0101): PIT trigger 1

6 (0110): PIT trigger 2

7 (0111): PIT trigger 3

8 (1000): FTM0 trigger

9 (1001): FTM1 trigger

10 (1010): FTM2 trigger

11 (1011): FTM3 trigger

12 (1100): RTC alarm

13 (1101): RTC seconds

14 (1110): Low-power timer trigger

15 (1111): High speed comparator 3 asynchronous interrupt
ADC0PRETRGSEL

ADC0 pre-trigger select

0 (0): Pre-trigger A selected for ADC0.

1 (1): Pre-trigger B selected for ADC0.
ADC0ALTTRGEN

ADC0 alternate trigger enable

0 (0): PDB trigger selected for ADC0.

1 (1): Alternate trigger selected for ADC0.
ADC1TRGSEL

ADC1 trigger select

0 (0000): External trigger

1 (0001): High speed comparator 0 asynchronous interrupt

2 (0010): High speed comparator 1 asynchronous interrupt

3 (0011): High speed comparator 2 asynchronous interrupt

4 (0100): PIT trigger 0

5 (0101): PIT trigger 1

6 (0110): PIT trigger 2

7 (0111): PIT trigger 3

8 (1000): FTM0 trigger

9 (1001): FTM1 trigger

10 (1010): FTM2 trigger

11 (1011): FTM3 trigger

12 (1100): RTC alarm

13 (1101): RTC seconds

14 (1110): Low-power timer trigger

15 (1111): High speed comparator 3 asynchronous interrupt
ADC1PRETRGSEL

ADC1 pre-trigger select

0 (0): Pre-trigger A selected for ADC1.

1 (1): Pre-trigger B selected for ADC1.
ADC1ALTTRGEN

ADC1 alternate trigger enable

0 (0): PDB trigger selected for ADC1.

1 (1): Alternate trigger selected for ADC1.
ADC2TRGSEL

ADC2 trigger select

0 (0000): External trigger

1 (0001): High speed comparator 0 asynchronous interrupt

2 (0010): High speed comparator 1 asynchronous interrupt

3 (0011): High speed comparator 2 asynchronous interrupt

4 (0100): PIT trigger 0

5 (0101): PIT trigger 1

6 (0110): PIT trigger 2

7 (0111): PIT trigger 3

8 (1000): FTM0 trigger

9 (1001): FTM1 trigger

10 (1010): FTM2 trigger

11 (1011): FTM3 trigger

12 (1100): RTC alarm

13 (1101): RTC seconds

14 (1110): Low-power timer trigger

15 (1111): High speed comparator 3 asynchronous interrupt
ADC2PRETRGSEL

ADC2 pre-trigger select

0 (0): Pre-trigger A selected for ADC2.

1 (1): Pre-trigger B selected for ADC2.
ADC2ALTTRGEN

ADC2 alternate trigger enable

0 (0): PDB trigger selected for ADC2.

1 (1): Alternate trigger selected for ADC2.
ADC3TRGSEL

ADC3 trigger select

0 (0000): External trigger

1 (0001): High speed comparator 0 asynchronous interrupt

2 (0010): High speed comparator 1 asynchronous interrupt

3 (0011): High speed comparator 2 asynchronous interrupt

4 (0100): PIT trigger 0

5 (0101): PIT trigger 1

6 (0110): PIT trigger 2

7 (0111): PIT trigger 3

8 (1000): FTM0 trigger

9 (1001): FTM1 trigger

10 (1010): FTM2 trigger

11 (1011): FTM3 trigger

12 (1100): RTC alarm

13 (1101): RTC seconds

14 (1110): Low-power timer trigger

15 (1111): High speed comparator 3 asynchronous interrupt
ADC3PRETRGSEL

ADC3 pre-trigger select

0 (0): Pre-trigger A selected for ADC3.

1 (1): Pre-trigger B selected for ADC3.
ADC3ALTTRGEN

ADC3 alternate trigger enable

0 (0): PDB trigger selected for ADC3.

1 (1): Alternate trigger selected for ADC3.

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data